Device Family: Intel® Arria® 10, Arria® V, Intel® Cyclone® 10, Intel® Cyclone® 10 GX, Cyclone® V, Stratix® V

Type: Errata

Area: Intellectual Property

Last Modified: July 19, 2017
Version Found: v16.1
Bug ID: FB: 477237;

Why are BAR addresses greater than 32 bits truncated to 32 bits on my Hard IP for PCI Express Avalon-MM variant?


Due to a problem with the Avalon-MM Hard IP core for PCI Express*, BAR addresses greater than 32 bits will be truncated to 32 bits only.  The upper bits will be set to zero.

This only affects the downstream direction Rxm ports when operating in 64-bit addressing mode. It does not affect the Txs ports or when operating in 32-bit addressing modes.


Please contact Intel® support ( for further information, and reference FB477237 in your service request.

This is scheduled to be fixed in a future Quartus® Prime software release.