Device Family: Intel® Arria® 10, Arria® II, Arria® V, Cyclone® IV GX, Cyclone® V GT, Cyclone® V GX, Cyclone® V ST, Cyclone® V SX, Intel® Stratix® 10, Stratix® IV GT, Stratix® IV GX, Stratix® V

Type: Answers

Area: Intellectual Property


Last Modified: May 19, 2017
IP: pci-express

Why do my non-posted TLPs not appear on the receive AVST interface?

Description

As described in the user guides for the Hard IP for PCI Express* Avalon-ST Interface, the rx_st_mask input will stall all non-posted TLPs when asserted.

Workaround/Fix

To work around this issue, ensure that the rx_st_mask input is deasserted when you wish to receive non-posted TLPs on the AVST Rx interface.