Device Family: Intel® Arria® 10, Arria® II, Arria® V, Arria® GX, Intel® Cyclone® 10 GX, Cyclone® IV GX, Cyclone® V GT, Cyclone® V GX, Cyclone® V ST, Cyclone® V SX, Intel® Stratix® 10, Stratix® II GX, Stratix® IV GT, Stratix® IV GX, Stratix® V GS, Stratix® V GT, Stratix® V GX

Type: Answers, Documentation

Area: Intellectual Property

Last Modified: September 14, 2017
Version Found: v4.0
Bug ID: FB: 493115;

What is the maximum payload size I can issue the PCI Express Hard IP on the Avalon-ST TX interface?


In Avalon-ST mode, the user logic is required to ensure that the TX TLP presented to the PCI* Express IP core is no larger than the negotiated Max Payload size.