Device Family: Intel® Stratix® 10

Type: Errata

Area: Intellectual Property


Last Modified: April 06, 2017
Version Found: v17.0
Bug ID: FB: 446297;
IP: SerialLite III Streaming

Stratix 10 SerialLite III Streaming Design Example unable to compile due to fPLL error.

Description

When using the Stratix® 10 SerialLite III IP core Streaming design example, the following fPLL error may be seen for depending on the transceiver reference clock frequency is being used.

Error: altera_sl3_fpll.altera_sl3_fpll: Violating K limits for auto mode. The most common occurence of this error is when refclk and output frequency combination can be synthesized in integer mode and user has selected fractional mode.

Workaround/Fix

To work around this issue, manually modify and regenerate the altera_sl3_fpll.ip file.

Using Qsys open and edit the example design FPLL file located in:

\ed_synth\altera_sl3_fpll.ip

de-select "Enable fractional mode" option, re-generate the IP and re-compile.

This problem will be fixed in a future release of the Quartus® Prime software.