Device Family: Intel® Stratix® 10 GX, Intel® Stratix® 10 SX

Type: Answers

Area: Intellectual Property


Last Modified: October 31, 2017
Version Found: v17.1
Bug ID: FB: 507044;
IP: Altera IOPLL, Altera LVDS SERDES

Why do I see redundant lvds_clk and loaden output ports when using IOPLL IP for LVDS external PLL mode?

Description

Due to a problem in the Intel® Quartus® Prime software version 17.1, generation of the IOPLL IP for external PLL LVDS mode results in two lvds_clk and loaden output ports. 

If the enable LVDS_CLK/LOADEN0 option is on, the RTL incorrectly includes five output ports.

Workaround/Fix

This problem is scheduled to be fixed in a future release of the Quartus Prime software.