For Arria® 10 and Stratix® 10 families. When RapidIO II IP Core is generated with the optional parameter "Enable transceiver control and status register" enabled, the provided simulation testbench will fail. The failing behavior is that the transceiver does not exit from reset, and rx_is_lockedtodata does not assert.
Device Family: Intel® Arria® 10, Intel® Stratix® 10
Area: Intellectual Property
Advice is to run the simulation without enabling the parameter "Enable transceiver control and status register" if affected.
This problem has been fixed starting in Quartus® Prime software version 17.0.