Device Family: Intel® Arria® 10, Intel® Stratix® 10

Type: Errata

Area: Intellectual Property


Last Modified: April 06, 2017
Version Found: v16.0
Version Fixed: v17.0
Bug ID: FB: 440420;
IP: RapidIO II (IDLE2 up to 6.25 Gbaud)

RapidIO II Simulation testbench failure when parameter "Enable Transceiver control and status register" is enabled.

Description

For Arria® 10 and Stratix® 10 families. When RapidIO II IP Core is generated with the optional parameter "Enable transceiver control and status register" enabled, the provided simulation testbench will fail. The failing behavior is that the transceiver does not exit from reset, and rx_is_lockedtodata does not assert.

Workaround/Fix

Advice is to run the simulation without enabling the parameter "Enable transceiver control and status register" if affected.

This problem has been fixed starting in Quartus® Prime software version 17.0.