Article ID: 000075375 Content Type: Troubleshooting Last Reviewed: 12/23/2022

Why might the Low Latency 40G and 100Gbps Ethernet MAC pause quanta time be shorter than expected?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Low Latency 40G 100G Ethernet
  • Ethernet
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    The IEEE standard 802.3 figure 31b-2 states that the pause timer should not be loaded with a received quanta value until the transmitter is idle.

    This spec aspect was not implemented in the Low Latency 40G and 100Gbps Ethernet MAC and PHY Megacore® Function flow control implementation.

    Therefore, if the TX is not idle when the pause quanta are loaded, the requested pause time may be shorter than expected.

    Resolution

    This problem is not currently scheduled to be fixed.

    Related Products

    This article applies to 4 products

    Stratix® V GS FPGA
    Stratix® V GT FPGA
    Stratix® V GX FPGA
    Intel® Arria® 10 FPGAs and SoC FPGAs

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