Device Family: Intel® Arria® 10, Stratix® V GS, Stratix® V GT, Stratix® V GX

Type: Errata

Area: Intellectual Property


Last Modified: March 22, 2017
Version Found: v15.1
Bug ID: FB: 396193;

Why might the Low Latency 40G and 100Gbps Ethernet MAC pause quanta time be shorter than expected?

Description

The IEEE standard 802.3 figure 31b-2, states that the pause timer should not be loaded with a received quanta value until the transmitter is idle.

This aspect of the spec was not implemented in the Low Latency 40G and 100Gbps Ethernet MAC and PHY Megacore® Function flow control implementation.

Therefore, if the TX is not idle when the pause quanta is loaded the requested pause time may be shorter than expected.

Workaround/Fix

This problem is not currently scheduled to be fix.