Device Family: Intel® Stratix® 10

Type: Answers

Area: Intellectual Property


Last Modified: September 19, 2017
Version Found: v17.1
Version Fixed: v17.1
Bug ID: FB: 492683;
IP: DSP

Error(19300): DSP WYSIWYG primitive "dafloater_i|s10fpdsp_block_0|sp_mult" has clock setting "adder_input_clock" that is not set to "none".

Description

Due to a problem with the Stratix® 10 Native Floating Point DSP IP in Quartus® Prime Pro software version 17.1 Stratix 10 ES Edition, you may observe the above error during compilation if you are using the multiplication mode.

Workaround/Fix

Do the following changes in the <ip_file_name>_altera_s10fpdsp_block_160_mdhrmmi.sv:

from

   .adder_input_clock("0")     //(line 28)

to

   .adder_input_clock("NONE")

 

This problem is fixed starting in Quartus Prime Pro v17.1 release software.