Device Family: Intel® Stratix® 10

Type: Answers, Errata

Area: Intellectual Property


Last Modified: November 22, 2017
Version Found: v17.1
Bug ID: FB: 501310;
IP: Avalon-MM Stratix 10 Hard IP for PCI Express

Error(13224): Verilog HDL or VHDL error at altera_pcie_s10_hptxs_tx.sv(<your line number>): index <your index> is out of range [<your range>] for address

Description

Due to a problem in the Intel® Quartus® Prime software, you will see this error with the Avalon®-MM Stratix® 10 Hard IP for PCI Express* if you do the following:

  • Select "Enable high performance bursting Avalon-MM slave interface (HPTXS)" 
  • And select "Enable mapping (HPTXS)"
  • AND select one of the first two choices
    • 1 page - 0 bits
    • 2 pages - 1 bit

Workaround/Fix

To work around this issue, choose one of the remaining 8 page mapping selections.

This problem is scheduled to be fixed in a future Quartus Prime software release.

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