Device Family: Intel® Arria® 10, Intel® Arria® 10 GT, Intel® Arria® 10 GX, Intel® Arria® 10 SX, Stratix® V E, Stratix® V GS, Stratix® V GX

Intel Software: Quartus Prime Pro, Quartus Prime Standard

Type: Answers

Area: Intellectual Property


Last Modified: February 08, 2017
Version Found: v12.0
Version Fixed: v16.0
Bug ID: FB: 363692;

Why does the Low Latency 40-100 Gbps Ethernet IP core hang or send erroneous packets for certain TX Avalon-ST interface conditions?

Description

The Low Latency 40-100 Gbps Ethernet IP core versions that predate the Quartus® Prime software v16.0 do not correctly handle the following conditions on the TX Avalon-ST interface. Any designs using the earlier versions of the IP core may hang or send erroneous packets if the below conditions occur:

  1. TX valid goes low within a valid packet between Start-of-Packet (SOP) and End-of-Packet (EOP) (client resets the valid signal during transmission of a multi-cycle packet)
  2. Packet size less than nine bytes
  3. Back to back SOPs
  4. Back to back EOPs

Although the Avalon-ST protocol allows these situations, the IP core does not support them.

Erroneous packets could have FCS or other errors, or could have less than the minimum IPG length.

 

Workaround/Fix

In the pre-16.0 versions of the IP core, you must modify the application to avoid these conditions. The IP core hang issue is fixed in the Low Latency 40-100 Gbps Ethernet IP core v16.0 and later. The IP core identifies these conditions as invalid inputs and flags them as errors.