The Low Latency 40-100 Gbps Ethernet IP core versions that predate the Quartus® Prime software v16.0 do not correctly handle the following conditions on the TX Avalon-ST interface. Any designs using the earlier versions of the IP core may hang or send erroneous packets if the below conditions occur:
- TX valid goes low within a valid packet between Start-of-Packet (SOP) and End-of-Packet (EOP) (client resets the valid signal during transmission of a multi-cycle packet)
- Packet size less than nine bytes
- Back to back SOPs
- Back to back EOPs
Although the Avalon-ST protocol allows these situations, the IP core does not support them.
Erroneous packets could have FCS or other errors, or could have less than the minimum IPG length.