Due to a problem with the DisplayPort IP core hardware demo example design (version 16.0 and earlier), an image may not be seen when the DisplayPort IP core sink is connected to an Intel® GPU. While the RX and TX MSA values may look correct, no image will display on the monitor. This is due to a mismatch between the clocking modes used by the Intel GPU and the DisplayPort IP core source. Intel GPUs use synchronous clocking, while the DisplayPort IP core source uses asynchronous clocking. This causes two problems with the hardware demo example design.
First, the hardware demo example design uses a fixed NVID value for the pixel clock recovery (PCR) module. This setting is intended for GPUs that use asynchronous clocking, and will not work with an Intel GPU.
Second, due to their clocking modes the Intel GPU sets bit 0 of the RX MSA MISC0 register to 1, while the DisplayPort IP core source sets bit 0 of the TX MSA MISC0 register to 0. While it is within spec for these bits to differ, the Nios® II software (specifically the EDID pass through code) expects RX MSA MISC0 to exactly match TX MSA MISC0, and disables the DisplayPort IP core source if there is a mismatch.