Device Family: Intel® Arria® 10, Arria® V, Cyclone® V, Stratix® V

Intel Software: Quartus Prime

Type: Answers

Area: Intellectual Property


Last Modified: October 07, 2016
Version Found: v16.0
Version Fixed: v16.1
Bug ID: FB: 407230;
IP: DisplayPort

Why does the DisplayPort IP core hardware demo example design fail to display an image when the DisplayPort IP core sink is connected to an Intel® GPU?

Description

Due to a problem with the DisplayPort IP core hardware demo example design (version 16.0 and earlier), an image may not be seen when the DisplayPort IP core sink is connected to an Intel® GPU. While the RX and TX MSA values may look correct, no image will display on the monitor. This is due to a mismatch between the clocking modes used by the Intel GPU and the DisplayPort IP core source. Intel GPUs use synchronous clocking, while the DisplayPort IP core source uses asynchronous clocking. This causes two problems with the hardware demo example design.

First, the hardware demo example design uses a fixed NVID value for the pixel clock recovery (PCR) module. This setting is intended for GPUs that use asynchronous clocking, and will not work with an Intel GPU.

Second, due to their clocking modes the Intel GPU sets bit 0 of the RX MSA MISC0 register to 1, while the DisplayPort IP core source sets bit 0 of the TX MSA MISC0 register to 0. While it is within spec for these bits to differ, the Nios® II software (specifically the EDID pass through code) expects RX MSA MISC0 to exactly match TX MSA MISC0, and disables the DisplayPort IP core source if there is a mismatch.

Workaround/Fix

First, modify the top level Verilog file to disable using a fixed NVID value for the PCR module. In the main project directory, modify the file a10_dp_demo.v to change one line,

From:

            defparam bitec_clkrec_i.FIXED_NVID = 1;

To:

            defparam bitec_clkrec_i.FIXED_NVID = 0;

Second, modify the Nios II software to ignore bit 0 when comparing the RX MSA MISC0 and TX MSA MISC0 registers. In the main project directory, modify the file main.c to change two lines,

From:

            rx_misc0 = IORD(btc_dprx_baseaddr(0), DPRX0_REG_MSA_MISC0) & 0xFFFF;

            tx_misc0 = IORD(btc_dptx_baseaddr(), DPTX0_REG_MSA_MISC0) & 0xFFFF;

To:

            rx_misc0 = IORD(btc_dprx_baseaddr(0), DPRX0_REG_MSA_MISC0) & 0xFFFE;

            tx_misc0 = IORD(btc_dptx_baseaddr(), DPTX0_REG_MSA_MISC0) & 0xFFFE;

After making these modifications, run the script build_sw.sh to rebuild the software project, then recompile the project in the Quartus® Prime software. Alternately, you can rerun the script runall.tcl, which will perform both of these steps for you.

Both of these problems have been fixed in the Quartus Prime software v16.1 DisplayPort hardware demo example design.