Device Family: Intel® Agilex™, Intel® Stratix® 10

Type: Answers

Area: HSIO


Version Found: v20.1
Bug ID: 14012146930

Why might my Intel® E-Tile Hard IP for Ethernet IP occasionally transmit duplicate or reordered words after power-up when used in Intel Stratix® 10 or Intel Agilex devices?

Description

Your Intel E-Tile Hard IP for Ethernet IP may occasionally transmit duplicate or reordered words after power-up when used in Intel Stratix 10 or Intel Agilex devices if the E-Tile Hard IP for Ethernet IP is in an AIB channel PLL clocked, multiple-channel, fractured master-slave configuration and the initialization reset sequence has not been followed.

Workaround/Fix

To reliably bring up your AIB channel PLL clocked, multiple-channel, fractured master-slave configured E-Tile Hard IP for Ethernet IP, you must implement the following sequence.

1.       Assert i_sl_csr_rst_n[3:0] and i_reconfig_reset

2.       Wait until your channel AIB PLL aib_pll_lock signal asserts

3.       De-assert the i_sl_csr_rst_n[master_channel] and i_reconfig_reset signals

4.       Wait 10ms

5.       De-assert the i_sl_csr_rst_n[slave_channels] signal

The requirement to sequence the de-assertion of the master-slave channel i_sl_csr_rst_n[3:0] signals will be added to a future revision of the E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs User Guide.