Device Family: Intel® Stratix® 10

Type: KDB Area

Area: HSIO


Last Modified: October 28, 2020
Version Found: v20.3
Bug ID: 18013555188

Why might I see an incorrect frequency PreSICE transceiver calibration clock on Intel® Stratix 10 devices?

Description

You might I see an incorrect frequency PreSICE transceiver calibration clock on Intel® Stratix® 10 devices if the Intel Quartus® Prime software has cached an old version of your OSC_CLK_1 Quartus Settings File (QSF) assignment. 

There is a PLL inside the FPGA that receives the clock from the OSC_CLK_1 pin and provides a 250-MHz calibration clock to PreSICE. This clock is used to calibrate all Intel Stratix 10 L-Tile and H-Tile device ATX PLLs, fPLLs, CDR/CMU PLLs, and PMAs. 

The clock source and frequency is chosen in the Intel Quartus Prime project Device and Pin Option GUI, or in the QSF file example assignment below. 

set_global_assignment -name DEVICE_INITIALIZATION_CLOCK OSC_CLK_1_125MHz

If you have recently changed your Configuration Clock Source setting in the Intel Quartus Prime software, an old version may be cached and used by the Intel Quartus software. This can result in an incorrect frequency calibration clock which may result in a higher Bit Error Rate (BER) on your Intel Stratix 10 L-Tile or H-Tile device transceiver channel.

Workaround/Fix

To work around this problem you can clean your Intel Quartus Prime database after you have changed your Configuration Clock Source setting. You can do this using the Intel Quartus Prime software menus as shown below. 

Project > Clean Project > All Revisions

You must then recompile your Intel Quartus Prime project.