Device Family: Intel® Stratix® 10 GX, Intel® Stratix® 10 MX, Intel® Stratix® 10 SX, Intel® Stratix® 10 TX

Intel Software: Quartus Prime Pro

Type: Answers

Area: HSIO

Last Modified: July 07, 2020
Version Found: v20.1
Version Fixed: v20.1
Bug ID: 1507971956

Why does the fPLL of the Intel® Stratix® 10 L- and H-tile device in fractional mode lose lock after calibration ?


When the fPLL of an Intel® Stratix® 10 L- and H-tile device is configured in fractional mode and its VCO frequency range is less than 7 GHz, fPLL registers may not be set to the calibrated value after fPLL power-up calibration or user-recalibration.


To work around the problem, reset fPLLs that lose lock after calibration by writing the following sequence to soft control registers through the fPLL Avalon Memory Mapped dynamic reconfiguration interface.

  1. Set register 0x4E0[1] to 1
  2. Set register 0x4E0[0] to 1
  3. Set register 0x4E0[0] to 0
  4. Set register 0x4E0[1] to 0 

You should tick the Enable Dynamic Reconfiguration, Enable Native PHY Debug Master Endpoint, and Enable Control and Status Registers options in the Intel Stratix 10 L- and H-tile device fPLL IP in order to write to the soft control registers above.