When Intel® Arria® 10 and Intel® Cyclone® 10 GX or Intel® Stratix® 10 Hard IP for PCI Express* is configured with Gen1/2/3 x1 mode, the master CGB in its triplet will be affected by the nPERST signal although it is not used for PCIe channels. When nPERST is asserted, it will hold the master CGB in reset state, then if any other non-PCIe channels are driven by this master CGB, the long transceiver calibration time will be seen and no toggling will appear on 'tx_pma_clkout' and 'tx_clkout' ports.
Device Family: Intel® Arria® 10, Intel® Cyclone® 10 GX, Intel® Stratix® 10
Last Modified: February 17, 2020
Version Found: v19.3
Bug ID: 16010026137