Device Family: Intel® Arria® 10, Intel® Cyclone® 10 GX, Intel® Stratix® 10

Type: Answers

Area: HSIO

Last Modified: February 17, 2020
Version Found: v19.3
Bug ID: 16010026137

Why are there long transceiver calibration time and no toggling on "tx_pma_clkout/tx_clkout" ports when nPERST pin of Hard IP for PCI Express* asserted?


When Intel® Arria® 10 and Intel® Cyclone® 10 GX or Intel® Stratix® 10 Hard IP for PCI Express* is configured with Gen1/2/3 x1 mode, the master CGB in its triplet will be affected by the nPERST signal although it is not used for PCIe channels. When nPERST is asserted, it will hold the master CGB in reset state, then if any other non-PCIe channels are driven by this master CGB, the long transceiver calibration time will be seen and no toggling will appear on 'tx_pma_clkout' and 'tx_clkout' ports.


To work around the problem, add the sentence in Quartus Settings File (.qsf) as below to avoid using the master CGB in the same triplet with active PCIe HIP to drive other non-PCIe channels.

"set_location_assignment HSSIPMACGBMASTER_1CB -to *|xcvr_fpll_a10_0|twentynm_hssi_pma_cgb_master_inst~O_MSTCGB_CORE0"