Device Family: Intel® Arria® 10, Intel® Stratix® 10

Type: Answers

Area: HSIO


Version Found: v19.2
Bug ID: 1808337843

How do I merge simplex transceiver PHYs inside the Intel® Quartus® Prime Platform Designer when using Intel Arria® 10 and Intel Stratix® 10 L-Tile/H-Tile devices?

Description

You can merge Intel simplex transceiver PHYs inside Intel Quartus Prime Platform Designer when using Intel Arria 10 and Intel Stratix 10 L-Tile/H-Tile devices with Wire-Level Expressions.

When merging Intel Arria 10 and Intel Stratix 10 L-Tile/H-Tile device simplex PHYs into a single duplex physical channel, one Intel Quartus Prime transceiver Fitter rule that must be followed is that the reconfig_address, reconfig_data, reconfig_write, and reconfig_read signals of the simplex TX and RX transceiver PHYs Avalon® Memory Mapped (AVMM) interface must be common.

Full transceiver merging rules are listed in the following user guides.

  • Intel Arria 10 Transceiver PHY User Guide
  • Intel Stratix 10 L- and H-Tile Transceiver PHY User Guide

The Intel Arria 10 and Intel Stratix 10 L-Tile/H-Tile device simplex TX and RX transceiver PHYs share a common address space. The Intel Quartus Prime Platform Designer will produce an address space overlap error message if the simplex TX and RX PHYs share the same address space. Correcting this address space overlap in the Intel Quartus Platform Designer causes it to insert logic between the transceiver TX and RX PHY AVMM interfaces which violates the Intel Quartus Prime transceiver Fitter rule requirement for a common AVMM bus. The design will fail to fit in the Intel Quartus Prime software.
 

Workaround/Fix

You can use Wire-Level Expressions in the Intel Platform Designer to allow the transceiver TX and RX PHYs to share the same address space.

The following example shows how you can use Wire-Level Expressions inside Intel Quartus Prime Platform Designer with a transmitter PHY named “TX”, and a receiver PHY named “RX”, that are both connected to a single Avalon-MM Pipeline Bridge.

TX.reconfig_address = mm_bridge_0.m0_address
TX.reconfig_read =mm_bridge_0.m0_read
TX.reconfig_write = mm_bridge_0.m0_write
TX.reconfig_writedata = mm_bridge_0.m0_writedata
RX.reconfig_address = mm_bridge_0.m0_address
RX.reconfig_read = mm_bridge_0.m0_read
RX.reconfig_write = mm_bridge_0.m0_write
RX.reconfig_writedata = mm_bridge_0.m0_writedata