Device Family: Intel® Stratix® 10 DX, Intel® Stratix® 10 MX, Intel® Stratix® 10 TX

Intel Software: Quartus Prime Pro

Type: Answers

Area: HSIO


Version Found: v19.1
Bug ID: 1507940192

Error(20731): For HSSI pin "xxx~pad", I/O standard "Differential LVPECL" is the only legal value.

Description

You may see this error message when you compile the golden example design from the Intel® Stratix® TX Signal Integrity Development Kit package under the Intel® Quartus® Prime Pro Edition software version 19.1 and later. This is because the golden example design is from the Intel® Quartus® Prime Pro Edition software version 18.1 with the Intel® Stratix® 10 E-tile transceiver reference clock I/O standard constrained as "LVDS". And the software I/O standard checking rule is changed in the Intel® Quartus® Prime Pro Edition software version 19.1 and later.

Workaround/Fix

To avoid this error, I/O standard of the Intel® Stratix® 10 E-tile transceiver reference clock should be constrained as "Differential LVPECL" in Assignment Editor or Quartus Settings File (.qsf) like the following.

set_instance_assignment -name IO_STANDARD "DIFFERENTIAL LVPECL" -to xxx