Device Family: Intel® Agilex™, Intel® Stratix® 10

Type: Answers

Area: HSIO


Last Modified: May 12, 2020
Version Found: v19.1
Version Fixed: v19.2
Bug ID: 1807851569

Error(15744): ( topology != EHIP_4CH_PTP_FEC )

Description

Due to a bug in the Intel® Quartus® Prime software version 19.1 and earlier, you may see the following Quartus Prime Fitter if instantiating two copies of the Intel E-Tile Hard IP for Ethernet Intel FPGA IP in Intel Stratix® 10 and Intel Agilex® transceiver E-Tile devices.

Error(15653): The Fitter cannot find a legal configuration for the following atoms. Update any outdated transceiver PHY IP cores, correct any illegal pin assignments, and then recompile your design.
Error(15744): In atom <path>|alt_ehipc3_0|alt_ehipc3_hard_inst|EHIP_CORE.c3_ehip_core_inst'
Error(15744): The settings must match one or more of these conditions:
Error(15744): ( topology != EHIP_4CH_PTP_FEC )

You may see this error when the two Intel E-Tile Hard IP for Ethernet are configured for 25GbE with PTP and RSFEC enabled, and are constrained to adjacent PTP blocks.

For example:

  • Two Intel E-Tile Hard IP for Ethernet configured for 25GbE with PTP and RSFEC enabled, constrained to use EHIP locations EHIP_CORE_0 and EHIP_CORE_1 may fail to fit
  • Two Intel E-Tile Hard IP for Ethernet configured for 25GbE with PTP and RSFEC enabled, constrained to use EHIP locations EHIP_CORE_2 and EHIP_CORE_3 may fail to fit
  • Two Intel E-Tile Hard IP for Ethernet configured for 25GbE with PTP and RSFEC enabled, constrained to use EHIP locations EHIP_CORE_0 and EHIP_CORE_2 may fit
  • Two Intel E-Tile Hard IP for Ethernet configured for 25GbE with PTP and RSFEC enabled, constrained to use EHIP locations EHIP_CORE_1 and EHIP_CORE_3 may fit
     

Workaround/Fix

This problem is fixed in Intel Quartus Prime software version 19.2 and later.