Device Family: Intel® Stratix® 10 DX, Intel® Stratix® 10 MX, Intel® Stratix® 10 TX

Type: How-To

Area: HSIO


Version Found: v19.3
Bug ID: 1507063824

Why isn’t there any PLLs usage if I compile the project with the Intel® Stratix® 10 E-tile transceiver channels ?

Description

It is correct you will see "Total PLLs" usage is 0 if you only instantiate Intel® Stratix® 10 E-tile transceiver channels in the design. The Intel® Stratix® 10 E-tile transceiver channel PLL would not be counted in the total PLLs summary. 

For example, if you use Intel® Stratix® 10 device 1ST280EY2F55, and instantiate 4 E-tile transceiver channels. After compilation, you will still see the “Total PLLs  0/64(0%)” in the flow summary of compilation report.

Actually all the PLL shows in the compilation report will be contributed by the Intel® Stratix® 10 IOPLL and H-tile transceiver PLLs. For Intel® Stratix® 10 device 1ST280EY2F55, the total 64 PLLs consist of 24xIOPLLs, 8xfPLLs of H-tile, 8xATX PLLs of H-tile transceiver, and 24 CDR PLLs of H-tile transceiver. No Intel® Stratix® 10 E-tile transceiver channel PLLs would be counted in. 

Workaround/Fix