Due to a problem in the Intel® Stratix®10 L-Tile/H-Tile transceiver RX Core FIFO, packet loss will be observed in RX interface if all the following conditions are met:
- Enhanced PCS transceiver RX Core FIFO is configured in 10GBASE-R mode
- Non-zero PPM between the TX link partner and the Intel Stratix 10 transceiver RX; and the Intel Stratix 10 RX CDR recovered clock is slower than the rx_coreclkin
- Resetting the transceiver PHY could trigger the problem
Typical applications affected by this issue are as following:
- 10GBASE-R, 10GBASE-R Low Latency or 10GBASE-R w/KR FEC presets in Native PHY IP
- 10GBASE-KR PHY IP
- 10GBASE-R Example Design of Low Latency Ethernet 10G MAC IP
When the problem happens, the IDLE characters are incorrectly inserted between packet preambles. The corrupted packet header cannot be recognized at MAC layer resulting in packet loss.