Device Family: Intel® Stratix® 10, Intel® Stratix® 10 GX, Intel® Stratix® 10 MX, Intel® Stratix® 10 SX, Intel® Stratix® 10 TX

Type: Answers

Area: HSIO


Version Found: v17.0
Bug ID: 1507015428
IP: 10GBASE-R PHY Intel FPGA IP

Why will packet loss be seen in Intel® Stratix® 10 L-Tile/H-Tile Transceivers 10G RX interface?

Description

Due to a problem in the Intel® Stratix®10 L-Tile/H-Tile transceiver RX Core FIFO, packet loss will be observed in RX interface if all the following conditions are met:

  • Enhanced PCS transceiver RX Core FIFO is configured in 10GBASE-R mode
  • Non-zero PPM between the TX link partner and the Intel Stratix 10 transceiver RX; and the Intel Stratix 10 RX CDR recovered clock is slower than the rx_coreclkin
  • Resetting the transceiver PHY could trigger the problem

Typical applications affected by this issue are as following:

    - 10GBASE-R, 10GBASE-R Low Latency or 10GBASE-R w/KR FEC presets in Native PHY IP

    - 10GBASE-KR PHY IP

    - 10GBASE-R Example Design of Low Latency Ethernet 10G MAC IP

When the problem happens, the IDLE characters are incorrectly inserted between packet preambles. The corrupted packet header cannot be recognized at MAC layer resulting in packet loss.

Workaround/Fix

Use either workaround below to avoid this problem.

  1. Use 0 PPM clocking between TX link partner and Intel® Stratix® 10 transceiver RX
  2. Use the 1G/2.5G/5G/10G Multi-rate Ethernet PHY IP as an alternative which implements similar RX Core FIFO functionality in core logic

This issue will be fixed in a future release of the Intel® Quartus® Prime Pro software.

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