Device Family: Intel® Arria® 10, Intel® Cyclone® 10 GX, Intel® Stratix® 10 GX, Intel® Stratix® 10 MX, Intel® Stratix® 10 SX, Intel® Stratix® 10 TX

Intel Software: Quartus Prime Pro, Quartus Prime Standard

Type: Answers

Area: HSIO


Last Modified: November 11, 2019
Version Found: v18.0
Bug ID: 1408163359
IP: Arria 10 Transceiver CMU PLL

Why does the transmitter jitter increase when resetting adjacent transceiver channels?

Description

You may observe increased jitter on an active transmitter channel with CMU PLL while resetting adjacent transceiver channels. This problem is caused when the CMU PLL high speed serial clock is enabled or disabled simultaneously on the adjacent channels, which causes a sudden local increase in the current consumption and jitter on the active transmitter channel.

Workaround/Fix

To work around this problem, use ATX PLL or fPLL instead of CMU PLL.

 

This problem will not be fixed in a future release of the Intel® Quartus® Prime Edition versions.