Device Family: Intel® Stratix® 10 MX, Intel® Stratix® 10 TX

Type: Errata

Area: Intellectual Property


Last Modified: Wed Feb 13 2019 06:34:25 GMT-0800
Version Found: v18.1 Update 1
Bug ID: 1507049399
IP: Interlaken IP Core (2nd Generation)

Why does my Interlaken (2nd Generation) Intel® Stratix® 10 FPGA IP with 25Gbps lanes fail timing closure when targeting an Intel® Stratix® 10 E-tile Engineering Sample (ES) device?

Description

Variants of the Interlaken (2nd Generation)  Intel® Stratix® 10 FPGA IP with 25Gbps lanes do not support Engineering Sample (ES) devices.

Workaround/Fix

In order to obtain the best “Quality of Result” for timing closure, launch Design Space Explorer II in the Intel® Quartus® Prime software and perform a seed sweep.