Device Family: Intel® Stratix® 10 GX, Intel® Stratix® 10 MX, Intel® Stratix® 10 SX, Intel® Stratix® 10 TX

Intel Software: Quartus Prime Pro

Type: Answers

Area: HSIO


Last Modified: December 20, 2019
Version Found: v18.1 Update 1
Version Fixed: v19.4
Bug ID: 1507123274

Why might my Intel® Stratix® 10 L-Tile or H-Tile transceiver device stop transmitting data when compiled with the Intel Quartus® Prime software versions 19.3 and earlier?

Description

Due to a problem in the Intel Stratix 10 L-Tile and H-tile transceiver calibration code firmware in the Intel Quartus Prime Pro software versions 19.3 and earlier, a transceiver calibration access may randomly power down the transmitter buffer.

A background calibration or user-recalibration of any channel, ATX PLL or fPLL within the transceiver tile may cause this.

When this happens, transceiver channel PMA register offset 0x112 is corrupted and cleared to 0x00. 0x112[0] represents cgb_powerdown and powers down the TX buffer when it is ‘0’.

This problem may occur in any transceiver L-Tile or H-Tile used in Intel Stratix 10 GX, SX, MX and TX devices compiled with the Intel Quartus Prime Pro software versions 19.3 and earlier.

Example transceiver configuration use applications that may be impacted are:

  1. Production H-Tile transceivers running at datarates ≥ 17.5Gbps which have background calibration enabled automatically by the Intel Quartus Prime Pro software.
  2. Any transceiver L-Tile or H-Tile design that has more than one used transceiver channel, and any user-recalibration process is performed.
  3. Any of the Intel IP listed below are affected.
Serial Protocol      Intel FPGA IPs
Ethernet                  H-tile Hard IP for Ethernet Intel FPGA IP
                                  25G Ethernet Intel FPGA IP
                                  Low latency 100G Ethernet Intel FPGA IP
                                  Low Latency 40G Ethernet Intel FPGA IP
                                  10GBASE-KR PHY Intel Stratix 10 FPGA IP
                                  1G/2.5G/5G/10G Multi-rate Ethernet Intel FPGA IP
Interlaken                Interlaken (2nd Generation) Intel FPGA IP
SerialLite                 Serial lite III Streaming Intel FPGA IP
Serial RapidIO        RapidIO II Intel FPGA IP*
JESD                        JESD204B Intel FPGA IP*
Audio/Video           Display Port Intel FPGA IP
                                  HDMI Intel FPGA IP
                                  SDI II Intel FPGA IP
Transceiver PHY    L-tile/H-tile Transceiver Native PHY Intel Stratix 10 FPGA IP*
 
* This IP does not perform a calibration itself, but you have the capability of performing one.
 
The Intel Stratix 10 Hard IP for PCI Express™ IP Core for Stratix 10 L-Tile and H-Tile devices is unaffected by this problem.
 

Workaround/Fix

This problem is fixed in the Intel Quartus Prime Pro software versions 19.4 and later.

If your design is compiled in the Intel Quartus Prime Pro software versions 19.1 or 19.3 you can install the following patch and reconfigure the FPGA. The patch updates the transceiver calibration code firmware using the Intel Quartus Prime Pro software programmer so you don’t need to recompile your design to regenerate your .SOF file.

Download patch 0.15 for Windows (quartus-19.3-0.15-windows.exe)
Download patch 0.15 for Linux (quartus-19.3-0.15-linux.run)
Download the Readme for patch 0.15 (quartus-19.3-0.15-readme.txt)

If your design is compiled in the Intel Quartus Prime Pro software version 19.2, contact your local Intel FAE or file an IPS Case using your My Intel support page.

If you are using programming files like .POF, .RBF, .RPD, .JIC that are generated from your .SOF file with Quartus Prime Pro software versions 19.3 and earlier, you must update them using either the Intel Quartus Prime Pro software version 19.4 Programmer or the Intel Quartus Prime Pro software version 19.1 or 19.3 with patch quartus-19.3-0.15 installed.

This problem is also described in the Intel® Stratix® 10 Device L-Tile and H-Tile Transceiver Calibration Code Firmware Update, Customer Advisory ADV1919.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/pcn/adv1919.pdf