Due to a problem in the Intel Stratix 10 L-Tile and H-tile transceiver calibration code firmware in the Intel Quartus Prime Pro software versions 19.3 and earlier, a transceiver calibration access may randomly power down the transmitter buffer.
A background calibration or user-recalibration of any channel, ATX PLL or fPLL within the transceiver tile may cause this.
When this happens, transceiver channel PMA register offset 0x112 is corrupted and cleared to 0x00. 0x112 represents cgb_powerdown and powers down the TX buffer when it is ‘0’.
This problem may occur in any transceiver L-Tile or H-Tile used in Intel Stratix 10 GX, SX, MX and TX devices compiled with the Intel Quartus Prime Pro software versions 19.3 and earlier.
Example transceiver configuration use applications that may be impacted are:
- Production H-Tile transceivers running at datarates ≥ 17.5Gbps which have background calibration enabled automatically by the Intel Quartus Prime Pro software.
- Any transceiver L-Tile or H-Tile design that has more than one used transceiver channel, and any user-recalibration process is performed.
- Any of the Intel IP listed below are affected.
Ethernet H-tile Hard IP for Ethernet Intel FPGA IP
25G Ethernet Intel FPGA IP
Low latency 100G Ethernet Intel FPGA IP
Low Latency 40G Ethernet Intel FPGA IP
10GBASE-KR PHY Intel Stratix 10 FPGA IP
1G/2.5G/5G/10G Multi-rate Ethernet Intel FPGA IP
Interlaken Interlaken (2nd Generation) Intel FPGA IP
SerialLite Serial lite III Streaming Intel FPGA IP
Serial RapidIO RapidIO II Intel FPGA IP*
JESD JESD204B Intel FPGA IP*
Audio/Video Display Port Intel FPGA IP
HDMI Intel FPGA IP
SDI II Intel FPGA IP
Transceiver PHY L-tile/H-tile Transceiver Native PHY Intel Stratix 10 FPGA IP*