In some Intel® Stratix® 10 design, 3V I/O bank will not be used as 3.0V signal input and output. And VCCIO3V will be connected to the power supply which is not 3.0V, but such as 1.8V or 1.2V which could share the same power plane with other banks.
Under this condition, the dedicated pins nPERST[L,R][0:2] have to be assigned non 3.0-V I/O standard.
So the fitter error may be encountered when nPERST[L,R][0:2] pins are assigned to non 3.0-V I/O standard without any additional assignments.