The Intel® Quartus® Prime Pro Edition software version 18.1 forces all banks in a Stratix® 10 L-tile or H-tile device to have the same VCCR_GXB and VCCT_GXB supply by default. If VCCR_GXB and VCCT_GXB in a transceiver tile have different voltage settings, the following error may be seen in compilation:
Error(18969): IO Banks < 1C 1D 1E 1F > are within same HSSI strip, Transceivers and PLLs placed inside these IO Banks needs to use the same power supply voltage. Transceivers and PLLs are using 1030 mv 1120 mv power supplies.
Error(12274): A critical error occurred while the periphery placement was committed to the atom netlist. The atom netlist is now invalid and the Fitter must be restarted.
The VCCR_GXB and VCCT_GXB pins within a Stratix 10 transceiver L-tile or H-tile bank must have the same voltage (either 1.03V or 1.12V). However, VCCR_GXB and VCCT_GXB of different banks within the same transceiver tile can have different voltages based on the configured transceiver data rates to further reduce power consumption of the transceiver tile.
For more information of VCCR_GXB and VCCT_GXB connections, refer to Intel Stratix 10 Device Family Pin Connection Guidelines.