Device Family: Intel® Arria® 10, Intel® Stratix® 10

Intel Software: Simulation

Type: Answers

Area: HSIO


Version Found: v16.1
Bug ID: 1608664233

Error: (vlog-7) Failed to open design unit file "./../../../rtl/address_decoder/address_decode/altera_avalon_st_handshake_clock_crosser_161/sim/altera_avalon_st_handshake_clock_crosser.v" in read mode.

Description

In Windows environment, you may find the following error message during simulation of Low Latency 10G MAC IP example design with Modelsim® when the maximum length of file path is beyond 260 characters

Error: (vlog-7) Failed to open design unit file "./../../../rtl/address_decoder/address_decode/altera_avalon_st_handshake_clock_crosser_161/sim/altera_avalon_st_handshake_clock_crosser.v" in read mode.

 

Workaround/Fix

To avoid the error, reduce the directory depth of simulation files.