Device Family: Intel® Stratix® 10

Type: Answers

Area: HSIO


Version Found: v17.1
Bug ID: FB: 549014;

Why is the RX Core FIFO full if PMA and PCS bonding mode is enabled in H-Tile Transceiver Native PHY Intel Stratix 10 FPGA IP?

Description

Due to a problem with Quartus® Prime Pro software version 17.1, the H-Tile Transceiver Native PHY Intel® Stratix® 10 FPGA IP may output incorrect rx_clkout frequency if the PMA and PCS bonding mode is enabled for non-PCIe mode. The incorrect rx_clkout frequency will cause the RX Core FIFO to become full.

Workaround/Fix

Use PMA only bonding for non-PCIe mode. This problem will be fixed in a future version of the Quartus Prime Pro software.