Device Family: Intel® Stratix® 10 GX, Intel® Stratix® 10 SX

Type: Answers, KDB Area

Area: HSIO

Why do I see “Couldn't grab settings for channel TX/RX/LINK|*“ in the Intel® Transceiver Toolkit when I have multiple tiles used in my Stratix® 10 design?


Due to lack of proper JTAG constraints, you may see the error “Couldn't grab settings for channel TX/RX/LINK|* “ in the Intel® Transceiver Toolkit when loading a design that has channels on multiple tiles. Due to the placement of the Native PHY soft logic, the issues are most commonly observed when you have multiple Native PHY instantiations on different tiles.


The solution is to constrain the reconfiguration clock fed to the reconfiguration port of the Native PHY. Confirm that ‘altera_reserved_tck’ and the clock connected to the reconfiguration clock port 'rcfg_clk' of the Native PHY have both been properly constrained and pass timing within TimeQuest. This clock is used for the Altera Debug Mater Endpoint (ADME) logic, which is used by Transceiver Toolkit to gain access to the transceiver's CSR space. It will be automatically constrained on your behalf as long as you have at least one other declared clock in your design via the SDC command 'create_clock'. To verify JTAG has been automatically constrained look through the output of quartus_fit for this message:

"Adding default timing constraints to JTAG signals.  This will help to achieve basic functionality since no such constraints were provided by the user."


Alternatively you may wish to be more accurate and manually constrain the JTAG clock.  To do this use the Quartus provided SDC timing template.


(1). Open SDC file with Quartus Prime Pro Edition ( File -> Open )

(2). Right click in the SDC file window to pop up menu

(3). Select 'Insert Templete'


(4). Select  'JTAG Signal Constraint' to insert constraints to SDC file.