Device Family: Intel® Stratix® 10

Type: Answers

Type: KDB Area

Area: HSIO

Last Modified: May 18, 2018
Version Found: v18.0
Bug ID: FB: 556484;

Why can’t I run RTL simulations of Intel® Stratix® 10 device fPLL VHDL models using Cadence® Xcelium® tools?


Intel Quartus® Prime software version 18.0 and earlier does not support simulation of the Intel Stratix 10 device fPLL using the Cadence Xcelium simulation tools.


To work around this problem you can use Cadence NCSim® or generate Verilog fPLL simulation models using the Quartus Prime software.

Support of fPLL RTL simulation using the Cadence Xcelium tools will be added to a future version of the Quartus Prime software.