Device Family: Intel® Stratix® 10

Intel Software: Quartus Prime Pro

Area: HSIO

Why isn't calibration busy status signal deasserted after user recalibration enabled for Intel® Stratix® 10 device?


During user recalibration with the reconfiguration interface, if the reconfig_write signal is pulled high for multiple clock cycles after the reconfig_waitrequest is deasserted, the calibration busy indicator which is either tx_cal_busy, rx_cal_busy or pll_cal_busy signal will be found not deasserted later. Then it will lead transceiver stalled.


Follow the waveform of writing to the reconfiguration interface in Intel®  Stratix® 10 L- and H-Tile user guide, the reconfig_write should be only one clock cycle high during every writing process after the reconfig_waitrequest is deasserted.

If you want to use calibration enable registers, make sure following the rules strictly to avoid unexpected calibration busy indicator behavior.