Device Family: Intel® Arria® 10, Arria® II GX, Arria® V, Cyclone® V, Stratix® IV, Stratix® V

Type: Answers

Area: HSIO


Last Modified: June 28, 2018
Bug ID: FB: 559648;

What is the meaning of the SerialLite II Deskew Tolerance in Table 3-1 of the SerialLite II IP Core User Guide (PDF)?

Description

The Max Deskew (Cycles) in Table 3-1 of the SerialLite II IP Core User Guide (PDF) means the maximum lane to lane skew the transceiver is able to accept.

Workaround/Fix

For example: If the Transfer Size is 4 then the Maximum Deskew time accepted by transceiver is 2 tx_coreclock clock cycles. In contrast if the Transfer Size is 1 then the Maximum Deskew time accepted by transceiver is 14 tx_coreclock clock cycles.