Device Family: Intel® Stratix® 10

Type: Answers, KDB Area


Last Modified: October 31, 2017
Version Found: v17.0
Bug ID: FB: 493096;

Critical Warning(18234): ATX PLLs *|xcvr_atx_pll_s10_htile_0|ct1_atx_pll_inst and *|xcvr_atx_pll_s10_htile_0|ct1_atx_pll_inst are 0 ATX PLLs apart. For ATX PLL VCO frequencies between 11.4 GHz and 14.4 GHz, when two ATX PLLs operate at the same VCO frequency (within 100 MHz), they must be placed 1 ATX PLLs apart.

Description

Compiling demo design with 4 GXT channels with data rate of 25.78125Gbps, and they are in the same bank. Using an ATX PLL as main PLL, and another ATX PLL as buffer. But Quartus® Prime Pro software will report critical warning as the following message.

Critical Warning(18234): ATX PLLs *|xcvr_atx_pll_s10_htile_0|ct1_atx_pll_inst and *|xcvr_atx_pll_s10_htile_0|ct1_atx_pll_inst are 0 ATX PLLs apart. For ATX PLL VCO frequencies between 11.4 GHz and 14.4 GHz, when two ATX PLLs operate at the same VCO frequency (within 100 MHz), they must be placed 1 ATX PLLs apart.

Workaround/Fix

This critical warning will be fixed in Quarts Prime Pro software in a future version.