Device Family: Intel® Stratix® 10 MX

Intel Software: Quartus Prime Pro

Type: Errata, How-To

Area: EMIF

Last Modified: February 13, 2020
Version Found: v19.1
Version Fixed: v20.1
Bug ID: 1507754625
IP: Stratix 10 External Memory Interfaces

Why doesn't the Intel® Stratix®10 MX HBM2 controller assert the AXI RVALID signal until the AXI RREADY is asserted from the user interface?


Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 19.4 and earlier, the Intel Stratix® 10 MX HBM2 IP doesn't assert the axi_<x>_<y>_rvalid signal until the axi_<x>_<y>_rready signal is asserted from the user interface. 

Note that <x> and <y> refer to channel and pseudo-channel number respectively.


For the Intel® Quartus® Prime Pro Edition Software version 19.3 and earlier, you can work around this problem by opening the file and changing the following:


(starting from line 423:)

assign ufi_rready = PHY_THROTTLE_RDATA_BRESP ?

//  (rready & rdata_fifo_almost_empty) : rready;   // before 

     (rdata_fifo_almost_empty) : rready;                    //after  

generate  if(PHY_THROTTLE_RDATA_BRESP) begin

// assign rvalid             = (rready & ~rdata_fifo_empty);  //before

    assign rvalid             = (~rdata_fifo_empty);                  //after 


This problem is scheduled to be fixed in a future release of the Intel Quartus Prime Pro Edition Software.