This is the expected behavior of the AXI* Switch when enabling pseudo BL8. The AXI* Switch needs to wait for the write data transfer of the transaction to complete before receiving the next write request. This will not impact the efficiency of the AXI* interface.
Device Family: Intel® Stratix® 10 MX
Last Modified: June 02, 2020
Version Found: v20.1
Bug ID: 1507991354
IP: Stratix 10 External Memory Interfaces