Device Family: Intel® Stratix® 10 MX

Intel Software: Quartus Prime Pro

Type: Answers

Area: EMIF


Last Modified: June 02, 2020
Version Found: v20.1
Bug ID: 1507998108
IP: Stratix 10 External Memory Interfaces

How does the transaction count operate after grant moves to the next master when using the Intel® Stratix®10 MX HBM2 controller with the AXI* Switch?

Description

When a master is not ready to issue the expected total transaction, grant will go to the next master, and the transaction counts will be refreshed to the original transaction counts.