Device Family: Intel® Stratix® 10

Intel Software: Quartus Prime Pro

Type: Answers

Area: EMIF


Version Found: v20.1
Bug ID: 1408170524
IP: Stratix 10 External Memory Interfaces, Memory Interfaces and Controllers

What may cause the Intel® Stratix® 10 DDR4 IP to violate the Exit Power Down to Refresh Minimum Delay (tXP)?

Description

Due to a problem in the Intel® Stratix® 10 DDR4 IP, the Exit Power Down to Refresh Minimum Delay (tXP) may be violated because the controller may not properly gate the Logical Rank Refresh request with the tXP timer which causes the request to execute immediately after exiting the Power Down. Therefore, the Logical Rank Refresh request may be ignored which may eventually lead to insufficient refreshes.

This problem may occur when the Enable Auto Power-Down option is turned ON, the memory format is selected as either RDIMM or LRDIMM, the Chip ID width is set to any 3DS configuration, and the Number of physical ranks per DIMM is set to a value greater than 1.

 

Workaround/Fix

To work around this problem, select the Enable User Refresh Control option and execute additional refresh requests.