Device Family: Intel® Stratix® 10

Intel Software: Quartus Prime Pro

Type: Answers

Area: EMIF


IP: Stratix 10 External Memory Interfaces

Why does the EMIF Debug Toolkit report that the Intel® Stratix® 10 DDR4 CKE*, ODT*, and RESET signals are uncalibrated?

Description

The EMIF Debug Toolkit doesn't deskew the Intel® Stratix® 10 DDR4 CKE* and ODT* signals directly because the DDR4 specification doesn't include them in the address / command parity calculation.

In the Address / Command Margins section, the EMIF Debug Toolkit reports all the signals that could possibly have a delay, but the margins are only reported on signals that are calibrated explicitly.
However, the CKE*, ODT*, and RESET signals are calibrated implicitly based on the CS* level / deskew, and therefore, the margins for these signals aren't reported.
The CKE*, ODT*, and RESET signals are programmed with the same delay setting value as the CS* signals.

Note that the character * refers to the memory rank number.

Workaround/Fix