Device Family: Intel® Stratix® 10, Intel® Stratix® 10 MX

Intel Software: Quartus Prime Pro

Type: Answers

Area: EMIF, Intellectual Property


Last Modified: Mon Apr 15 2019 22:45:00 GMT-0700
Version Found: v19.1
Bug ID: 1409184691

Why does the High Bandwidth Memory (HBM2) Interface IP example design in the Intel® Stratix® 10 MX FPGA show min pulse width violation?

Description

Due to a problem in the Intel® Quartus® Prime Pro Edition software version 19.1 and earlier, you may see the min pulse width violation if you create an example design for the High Bandwidth Memory (HBM2) Interface IP targeting the Intel Stratix® 10 MX FPGA. 

Workaround/Fix

To work around this problem, download and install the Intel® Quartus® Prime Pro Edition software version 19.1 patch 0.04 from the appropriate link below. After installing the patch, follow the steps shown in the Readme file.

This problem is scheduled to be fixed in a future release of the Intel Quartus Prime Pro Edition software.