Device Family: Intel® Stratix® 10 MX

Intel Software: Quartus Prime Pro

Type: Answers

Area: EMIF


Last Modified: July 09, 2019
Version Found: v19.1
Bug ID: 1507296133

Why does the Intel® Stratix® 10 HBM2 IP calibration success signal stay low at Tj less than 0°C ?

Description

The minimum operating temperature for HBM2 DRAM is 0°C. When the Intel® Stratix® 10 MX FPGAs must be configured at less than 0°C, the HBM2 controller will read the junction temperature (Tj) using the TSD (temperature sense diode) and will hold the controller in reset.  The local_cal_success signal and AXI_*_ready signals won't be asserted until Tj reaches 0°C or greater.

Workaround/Fix