Device Family: Intel® Stratix® 10

Intel Software: Quartus Prime Pro

Type: Answers

Area: EMIF


Version Found: v19.1
Bug ID: 1507205476
IP: Stratix 10 External Memory Interfaces

What are the calibration sequences for the Intel® Stratix® 10 EMIF IP?

Description

After FPGA device configuration, below are the calibration sequences for the Intel® Stratix® 10 EMIF IP.

For the non-HPS EMIF IP, the sequences are on-chip termination (OCT) calibration, I/O PLL calibration, and then the EMIF calibration.

For the HPS EMIF IP, the OCT / PLL / EMIF calibration sequences are done in the HPS-first phase and then the rest of the FPGA is done in the FPGA-first mode.

The I/O PLL calibration for non-EMIF PLLs is also split between before user-mode entry and after user-mode entry depending on the configuration of the PLL itself.  If the PLL uses internal compensation modes, it is calibrated before user-mode entry.  If it uses core compensation modes, it is calibrated after user-mode entry.  All of this happens before EMIF calibration though, which is done entirely in user-mode.