Device Family: Intel® Stratix® 10

Intel Software: Quartus Prime Pro

Type: Errata, How-To

Area: EMIF


Version Found: v19.3
Version Fixed: v20.1
Bug ID: 1409872793
IP: Altera PHYLite for Parallel Interfaces

Warning(332035): No clocks found on or feeding the specified source node

Description

Due to a problem in the Intel® Stratix® 10 PHYLite IP in the Intel Quartus® Prime Software version 19.3 and earlier, you may see the following warning messages when there are multiple instances of the PHYLite IP in the project:

Warning(332035): No clocks found on or feeding the specified source node: <node_name_path>|inst~_Duplicate~out_phy_reg 

Warning(332035): No clocks found on or feeding the specified source node: <node_name_path>|inst~_Duplicate~out_phy_reg__nff 

Warning(332087): The master clock for this clock assignment could not be derived.  Clock: <clock_name> was not created. 

 

Additionally, the Unconstrained Paths report in the TimeQuest timing analyzer shows that the PHYLite clocks are illegal.

 

In the original PHYLite IP-generated SDC file, you will see the following lines:

set write_fifo_clk [get_keepers -nowarn ${inst}*|core|arch_inst|group_gen[$i_grp_idx].u_phylite_group_tile_14|lane_gen[*].u_lane|inst~out_phy_reg]

set write_fifo_clk_neg [get_keepers -nowarn ${inst}*|core|arch_inst|group_gen[$i_grp_idx].u_phylite_group_tile_14|lane_gen[*].u_lane|inst~out_phy_reg__nff]

 

The problem is that the SDC file isn't including the inst~_Duplicate~out_phy_reg and inst~_Duplicate~out_phy_reg__nff node names (as described in the warnings above).

Workaround/Fix

To work around this problem, change the ~ to * in the |inst*out_phy_reg and the |inst*out_phy_reg__nff nodes in the PHYLite IP-generated SDC file as shown below:  

set write_fifo_clk [get_keepers -nowarn ${inst}*|core|arch_inst|group_gen[$i_grp_idx].u_phylite_group_tile_14|lane_gen[*].u_lane|inst*out_phy_reg]

set write_fifo_clk_neg [get_keepers -nowarn ${inst}*|core|arch_inst|group_gen[$i_grp_idx].u_phylite_group_tile_14|lane_gen[*].u_lane|inst*out_phy_reg__nff]

This will include the inst~_Duplicate~out_phy_reg and inst~_Duplicate~out_phy_reg__nff node names, and the appropriate SDC constraints will be created.

 

This problem is fixed starting with the Intel® Quartus® Prime Pro Edition software version 20.1.