Due to a problem in the eSRAM Intel® FPGA IP in the Intel Quartus® Prime Pro software versions 19.3 and earlier, if your project is using two eSRAMs, you will see this warning message after analysis and synthesis :
Warning(16817): Verilog HDL warning at iopll.v(30): overwriting previous definition of iopll module
If the two eSRAMs have the same PLL parameters (PLL reference clock frequency and PLL desired clock frequency), the warning message can be ignored.
If the two eSRAMs have different PLL parameters, after compilation they will be set to the same PLL frequencies taken from one of the eSRAM IP parameters. Refer to the Quartus Fitter report > Plan Stage > PLL Usage Summary to observe the implemented eSRAM I/O PLL frequencies.