A fitter error with a message similar to this may be seen when using the Intel® Stratix® 10 EMIF IP if there are PLL reference clock connections spanning across more than 8 I/O banks :
Internal Error: Sub-system: CPLL, File: /quartus/periph/cpll/refclk_gen6_param_util.cpp, Line: 387
Reference clock network for 12 tiles is not currently supported!
This is typically seen on larger Intel Stratix 10 devices with multiple external memory interfaces placed in an I/O column sharing core clocks or the PLL reference clock. Note that when sharing core clocks, the PLL reference clock is also distributed in the core clocks sharing bus that connects between the core clock master and slaves.