Device Family: Arria Series, Cyclone Series, MAX Series, Stratix Series

Intel Software: Quartus Prime Standard

Type: How-To

Area: EMIF


Version Found: v16.0
Bug ID: 1507279928
IP: memory-interfaces-with-uniphy

How can the read data path read_capture_clk signal of the Intel® UniPHY IP be probed on a test pin by using ECO?

Description

When debugging the Intel® UniPHY IP, it may be useful to probe the read_capture_clk signal to investigate the DQS enable functionality gating the DQS signal.

One solution is to probe the read_capture_clk signal on a test pin by performing the following engineering change order (ECO) steps:

1. Open Chip Planner, find a pin which you will use as a test pin. Then right click and select Create Atom, set type as output and name it (e.g. eco_atom_dqs).

2. Double click the atom to the pin's Resource Property Editor page and select the pin's I/O standard.

3. In the Output buffer, right click Edit Connection > Other and enter the full path of the read_capture_clk in the Signal Name (e.g.  |ddr3ip_example|ddr3ip_example_if0:if0|ddr3ip_example_if0_p0:p0|ddr3ip_example_if0_p0_memphy:umemphy|ddr3ip_example_if0_p0_read_datapath:uread_datapath|read_capture_clk_div2[5]).

4. Run ECO compilation flow.