In the Intel® Quartus® Prime software, the buffer size of the Platform Designer interconnect depends on two factors:
1. Maximum pending read transactions from an Avalon slave IP (for instance: Intel Arria® 10 EMIF IP)
2. Burstcount width of the Avalon MM interface
However, the maximum pending read transactions of the EMIF IP can't be changed and is set to a fixed value of 64 to maximize the EMIF efficiency.