The following fitter error may be seen in a project implementing two independent External Memory Interfaces Intel® Cyclone®10 DDR3 IP placed in I/O banks in the same I/O column which are sharing a reset signal connected to their global_reset_n ports but not sharing clocks :
Error(18090): External memory and PHYLite interfaces must share common clock and reset signals when constrained to the same I/O column. The following conflicting signals were found:
Info(18087): Signal: <emif_0_path>|arch|arch_inst|non_hps.core_clks_rsts_inst|global_reset_n_int
Info(18087): Signal: <emif_1_path>|arch|arch_inst|non_hps.core_clks_rsts_inst|global_reset_n_int
In this configuration, the DDR3 IP global_reset_n ports must be connected to the same reset signal. Note that DDR3 clock sharing (pll reference clock or core clocks) is optional.