Device Family: Intel® Cyclone® 10 GX

Intel Software: Quartus Prime Pro

Type: Answers

Area: EMIF


Version Found: v19.1
Bug ID: 1807922230

Error(18090): External memory and PHYLite interfaces must share common clock and reset signals when constrained to the same I/O column

Description

The following fitter error may be seen in a project implementing two independent External Memory Interfaces Intel® Cyclone®10 DDR3 IP placed in I/O banks in the same I/O column which are sharing a reset signal connected to their global_reset_n ports but not sharing clocks :

Error(18090): External memory and PHYLite interfaces must share common clock and reset signals when constrained to the same I/O column. The following conflicting signals were found: 

Info(18087): Signal: <emif_0_path>|arch|arch_inst|non_hps.core_clks_rsts_inst|global_reset_n_int 

Info(18087): Signal: <emif_1_path>|arch|arch_inst|non_hps.core_clks_rsts_inst|global_reset_n_int

In this configuration, the DDR3 IP global_reset_n ports must be connected to the same reset signal. Note that DDR3 clock sharing (pll reference clock or core clocks) is optional.

Workaround/Fix

To work around this fitter error:

  1. Ensure that the Intel® Cyclone® 10 DDR3 IP parameter Diagnostics > Example Design > Enable In-System-Sources-and-Probes (ISSP) is not selected.
  2. If there is an ISSP assignment in the project .qsf file as shown below, comment it out or delete it. 

set_global_assignment -name VERILOG_MACRO "ALTERA_EMIF_ENABLE_ISSP=1"

The enabling of ISSP in a project causes the DDR3 IP reset signals to be interpreted by the Intel Quartus® Prime Pro Edition Software as being different, even though they are connected to the same signal source.