Device Family: Intel® Arria® 10

Type: Answers

Area: EMIF

Last Modified: September 11, 2019
Version Found: v19.1
Bug ID: 1607598066
IP: Arria 10 External Memory Interfaces

Error(18090): External memory and PHYLite interfaces must share common clock and reset signals when constrained to the same I/O column.


Due to a problem in the Intel® Quartus® Prime software version 19.2 or earlier, you may see the fitter error message when you aren't sharing the same clock and reset signals across multiple Intel Arria® 10 EMIF IP in the same I/O column. This message is incorrect, and you can follow the guidelines as described in the Intel Arria 10 EMIF IP User Guide. To place multiple interfaces in the same I/O column, you must ensure that the global reset signals (global_reset_n) for each individual interface all come from the same input pin or signal.



This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime software.