Device Family: Intel® Arria® 10

Type: Answers

Area: EMIF

Last Modified: January 08, 2019
Version Found: v18.1 Update 1
Bug ID: FB: 2205700453;
IP: Altera PHYLite for Parallel Interfaces

Error(13149): EMIF/PHYLite systems sharing a PLL reference clock do not have identical reset inputs for following io_aux atoms


When you implement both an Intel® Arria® 10 External Memory Interfaces IP and an Intel Arria 10 PHYLite IP that are sharing the PLL reference clock and reset in the same I/O column, you may see this fitter error.



To work around this problem, tie the Intel® Arria® 10 PHYLite IP reset port to "1".  This problem is planned to be fixed in a future release of the Intel Quartus® Prime software.