Device Family: Intel® Arria® 10, Intel® Cyclone® 10 GX, Intel® Stratix® 10

Intel Software: Quartus Prime Lite, Quartus Prime Pro, Quartus Prime Standard

Type: Answers

Area: EMIF


Version Found: v17.1
Bug ID: 2205746451
IP: Arria 10 External Memory Interfaces, Stratix 10 External Memory Interfaces

Can the MMR interface be used in conjunction with the Efficiency Monitor in the External Memory Interface Intel® FPGA IP?

Description

Due to a restriction in the Intel® Quartus® Prime software, it is not possible to enable the Memory Mapped Configuration and Status Register (MMR) interface in conjunction with the Efficiency Monitor when implementing DDR3 or DDR4 interfaces using the External Memory Interface Intel FPGA IP for Intel Arria® 10, Intel Cyclone® 10 GX or Intel Stratix® 10 devices.

Enabling both options will result in an error like that shown below :

Error: Interface must have an associated clock

Workaround/Fix

There is no planned fix for this restriction.