Device Family: Arria® V GT, Arria® V GX, Arria® V ST, Arria® V SX, Cyclone® V

Intel Software: Quartus Prime Standard

Type: Answers

Area: EMIF


Version Found: v13.0
Bug ID: 1306697631
IP: LPDDR2 SDRAM Controller with UniPHY

Are there any factors that can affect the efficiency performance of the UniPHY LPDDR2 IP?

Description

The LPDDR2 IP has a feature called DQS tracking which affects the bandwidth available for the user application. DQS tracking is required to maintain the correct signal timing to ensure that the data from an LPDDR2 read access is sampled correctly in the FPGA at all memory clock frequencies.

DQS tracking is comprised of two parts :

  • Sample : A DQS sample is taken after every memory refresh cycle
  • Update : When sufficient samples have been taken, a DQS tracking update cycle occurs which can take several microseconds.  Its duration is dependent on the width of the interface as the DQS I/O delays are updated sequentially. During a DQS tracking update,  accesses on the LPDDR2 controller Avalon bus are idle. The IP doesn't allow the user to schedule the DQS tracking update.

You are strongly recommended to perform RTL simulations of your access patterns to assess the effects of DQS tracking and any impact on your system functionality or efficiency.

If LPDDR2 is unsuitable for your application, it is recommended to consider the next lowest power external memory solution which is DDR3L, where the DQS tracking requirement is frequency dependent and there are options to disable it as described in this KDB.

Workaround/Fix